Field of the Disclosure
The present disclosure relates generally to processing systems using paged memory and more particularly to performing memory page accesses at a processor.
Description of the Related Art
To simplify programming and enhance processing efficiency, some processors employ a memory management technique referred to as memory paging. An operating system at the processor assigns an executing program contiguous memory spaces, referred to as memory pages, in a virtual address space. This allows the executing program to address virtual address spaces larger than the physical address space of the processor's system memory, and also isolates the physical address space from other executing programs, thereby simplifying program design. In order to enhance memory access speeds, a processor can move memory pages between different levels of the processor's memory hierarchy. Because of limitations on the physical memory space, movement of a memory page into a given level of the memory hierarchy (e.g., a level 3 (L3) cache) sometimes requires replacement of another memory page at that level. Conventional algorithms for selecting the memory page, such as a least-recently-used (LRU) based selection, often provide sub-optimal results, particularly in situations with variations in how different programs access memory, changes in operating conditions, and other factors.